Markets are bidding up Intel, AMD, and ARM on the CPU rally. Wrong layer.
The Rambus print this afternoon told us the bottleneck isn’t CPU silicon. It’s the OSAT layer behind the CPU. RMBS guided supply tight into 2027, with product revenue capped not by demand but by back-end assembly capacity at their packaging partners.
OSAT means Outsourced Semiconductor Assembly and Test. It’s the back-end of chip manufacturing, where wafers get diced, packaged, and tested before shipping. CoWoS is technically an OSAT function too, just done in-house at TSMC. Same physical constraint, same multi-year lead time to expand. When CoWoS gates GPU shipments and OSAT gates DIMM interface chips, the entire memory subsystem is bottlenecked at the same layer of the supply chain.
That layer is what NVIDIA locked up
NVIDIA negotiates HBM, LPDDR, CoWoS substrate, and OSAT capacity as one bundled allocation. They own the controller IP on Grace and Vera. They co-developed SOCAMM. When NVIDIA places an order, the entire stack gets allocated together because nobody wants to lose the GPU business.
x86 enterprise is the opposite. Five or six independent supply chain links, each negotiating allocation separately. CPU silicon is fine. Everything below it competes for shared OSAT capacity that’s already pre-booked by NVIDIA and the HBM trio.
The bear case on Grace for two years was that x86 enterprise wouldn’t switch because of recompilation cost and tooling friction. That argument assumed equal availability. If the x86 path is gated by DIMM availability into 2027 and the Grace path isn’t, the friction calculus inverts.
The question stops being “is it worth recompiling for Grace” and becomes “can I even buy enough DIMMs to scale my fleet by Q3.” Hyperscalers will pick the available path every time.
Turin can be the best server CPU ever made. It doesn’t matter if customers can’t get DIMMs to populate the slots.
$rmbs $intc $amd $NVDA
The Rambus print this afternoon told us the bottleneck isn’t CPU silicon. It’s the OSAT layer behind the CPU. RMBS guided supply tight into 2027, with product revenue capped not by demand but by back-end assembly capacity at their packaging partners.
OSAT means Outsourced Semiconductor Assembly and Test. It’s the back-end of chip manufacturing, where wafers get diced, packaged, and tested before shipping. CoWoS is technically an OSAT function too, just done in-house at TSMC. Same physical constraint, same multi-year lead time to expand. When CoWoS gates GPU shipments and OSAT gates DIMM interface chips, the entire memory subsystem is bottlenecked at the same layer of the supply chain.
That layer is what NVIDIA locked up
NVIDIA negotiates HBM, LPDDR, CoWoS substrate, and OSAT capacity as one bundled allocation. They own the controller IP on Grace and Vera. They co-developed SOCAMM. When NVIDIA places an order, the entire stack gets allocated together because nobody wants to lose the GPU business.
x86 enterprise is the opposite. Five or six independent supply chain links, each negotiating allocation separately. CPU silicon is fine. Everything below it competes for shared OSAT capacity that’s already pre-booked by NVIDIA and the HBM trio.
The bear case on Grace for two years was that x86 enterprise wouldn’t switch because of recompilation cost and tooling friction. That argument assumed equal availability. If the x86 path is gated by DIMM availability into 2027 and the Grace path isn’t, the friction calculus inverts.
The question stops being “is it worth recompiling for Grace” and becomes “can I even buy enough DIMMs to scale my fleet by Q3.” Hyperscalers will pick the available path every time.
Turin can be the best server CPU ever made. It doesn’t matter if customers can’t get DIMMs to populate the slots.
$rmbs $intc $amd $NVDA
Show More
